Static random access memories (SRAM) are commonly used in integrated circuits. Embedded SRAM is particularly popular in high speed communication, image processing and system on chip (SOC) applications. SRAM cells have the advantageous feature of holding data without requiring a refresh. FIG. 1 is a circuit diagram of a six transistor single-port SRAM cell circuit 10. Typically, a SRAM cell includes two pass-gate transistors (labeled PG), through which a bit can be read from or written into the SRAM cell. The basic cell 10 includes two cross-coupled inverters including two pull-up (PU) and two pull-down (PD) transistors, which form a data storage latch. The pass gate (PG) transistors are coupled between the differential bitlines (BL and BLB) for reading a bit from and/or writing a bit to the SRAM cell latch. The gates of the pass-gate transistors are controlled by a wordline. Another type of SRAM cell is referred to as dual port SRAM cell, which includes four pass-gate transistors.
In deep sub-micron technology, device mismatch and lowered wordline voltage levels affect the write capabilities of the SRAM cell. That is, the Von (Vgs−Vth) of the program transistors (PG) is decreased, degrading the write capability of the SRAM cell. For this reason, during a write operation a negative pulse is provided to the bitline (BL/BLB) to improve Von of the PG transistors.
FIG. 2 is a circuit diagram of one conventional approach to providing the negative pulse to the bitline. This method relies on capacitive coupling through an inverter to pull down the BL voltage to a negative value. As shown in FIG. 2, a positive pulse is provided to an inverter 12, which is coupled to the BL (labeled as NBL to represent a negative bitline voltage) through capacitor 14. Transistor 16 is responsive to signal RESET to reset the bitline to ground after the write operation. The voltage that is coupled to the bitline in FIG. 2 is tied to the supply voltage VDD of the inverter 12. As such, if the supply voltage VDD of the inverter 12 is lowered, the magnitude of the negative voltage pulse is also lowered. This relationship is shown in FIG. 3. At lower VDD levels, a higher, not lower, negative voltage pulse magnitude is needed to improve write capability. Moreover, the higher magnitude negative voltage under higher VDD conditions, as shown in FIG. 3, can disturb data values on unselected cells.
An improved biasing method for write operations in SRAM cells is desired.